The Influence of DSP Processor Architectures on Code Compilation Difficulties

Today's DSP designers until recently were faced with the task of coding increasingly complex applications using inefficient compilers or tedious handgenerated assembly code. To make matters worse the products demanded low cost, extremely high performance and low power especially in the area of wireless communications and consumer markets. This paper examines the architectural features of several popular DSP processors over the past 10 years, hilighting code compilation for performance, price, and power. Characteristics of a recently announced DSP processor will be examined, to show the positive impact of the architecture on the code compilation task. The goals of this paper are to show how DSP processors have evolved over the past decade and to present some evidence that current architectures are much improved. This research is important for developing a general methodology for code compilation for embedded DSP programmable processors with performance, price and power constraints.